16th International Conference on VLSI Design: concurrently with the 2nd International Conference on Embedded Systems Design
The 87 papers in this proceedings of the January 2003 conference reflect the theme of convergence in system-on-a-chip design and the increasing need to design and verify hardware and software simultaneously. The collection explores on-going research in field programmable gate arrays, MOS technology, VLSI processors, memory technology, test optimization, low power technologies, and reconfigurable system software. Topics include interfacing cores with on-chip packet-switched networks, the...
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Personal and portable : the evolving definition3Living at the edge4India - building the tall, thin VLSI engineer5Advances in VLSI design and product development challenges6High level modeling and validation methodologies for embedded systems : bridging the productivity gap9Design of deep sub-micron CMOS circuits15Testing embedded cores and Socs - DFT, ATPG and BIST solutions17Specification and design of multi-million gate SOCs18ESD reliability challenges of RF/mixed signal design and processing20System support for embedded applications22Narrow band noise suppression scheme for improving signal to noise ratio25A path sensitization technique for testing of switched capacitor circuits30A novel RF front-end chipset for ISM band wireless applications36Development of 2.4 GHz RF transceiver front-end chipset in 0.25 [mu]m CMOS42Comparison of heuristic algorithms for variable partitioning in circuit implementation51Timing minimization by statistical timing hMetis-based partitioning58An efficient practical heuristic for good ration-cut partitioning64An efficient multi-level partitioning algorithm for VLSI circuits70Low power technology mapping for LUT based FPGA - a genetic algorithm approach79Routability prediction for field programmable gate arrays with a routing hierarchy85A fast macro based compilation methodology for partially reconfigurable FPGA designs91Detailed analysis of FIBL in MOS transistors with high-k gate dielectrics99Effect of scaling on the non-quasi-static behaviour of the MOSFET for RF IC's105Small signal characteristics of thin film single halo SOI MOSFET for mixed mode applications110A new approach to analyze a sub-micron CMOS inverter116Optimization of 1.8V I/O circuits for performance, reliability at the 100nm technology node122Application of look-up table approach to high-k gate dielectric MOS transistor circuits128Effects of multi-cycle sensitization on delay tests137Exclusive test and its applications to fault diagnosis143A fault-independent transitive closure algorithm for redundancy identification149Exploiting ghost-FSMs as a BIST structure for sequential machines155Design of a universal BIST (UBIST) structure161SPaRe : selective partial replication for concurrent fault detection in FSMs167Design of a 2D DCT/IDCT application specific VLIW processor supporting scaled and sub-sampled blocks177Design of a high speed string matching co-processor for NLP183A new reactive processor with architectural support for control dominated embedded systems189Processing and scheduling components in an innovative network processor architecture195A novel architecture for lifting-based discrete wavelet transform for JPEG2000 standard suitable for VLSI implementation202A memory efficient 3-D DWT architecture208Electrical model for program disturb faults in non-volatile memories217Substrate bias effect on cycling induced performance degradation on flash EEPROMs223Analyzing soft errors in leakage optimized SRAM design227The impact of bit-line coupling and ground bounce on CMOS SRAM performance234Formal verification using bounded model checking : SAT versus sequential ATPG engines243Automating formal modular verification of asynchronous real-time embedded systems249High level synthesis from sim-nML processor models255Multiple trigonometric approximation of sine-amplitude with small ROM size for direct digital frequency synthesizers261Embedded tutorial : embedding security in wireless embedded systems269Cryptosystem designed for embedded system security271A pipeline architecture for encompression (encryption + compression) technology277VLSI implementation of online digital watermarking technique with difference encoding for 8-bit gray scale images283Ultra low-leakage power strategies for sub-1 V VLSI : novel circuit styles and design methodologies for partially depleted silicon-on-insulator (PD-SOI) CMOS technology291Resource allocation and binding approach for low leakage power297Synthesis of dual-V[subscript T] dynamic CMOS circuits303A low-voltage low power CMOS companding filter309An adaptive supply-voltage scheme for low power self-timed CMOS digital design315A methodology for accurate modelling of energy dissipation in array structures320Channel width test data compression under a limited number of test inputs and outputs329Static test compaction for full-scan circuits based on combinational test sets and non-scan sequential test sequences335Genetic algorithm based test scheduling and test access mechanism design for system-on-chips341Mutual testing based on wavelet transforms347New graphical I[subscript DDQ] signatures reduce defect level and yield loss353Immediate neighbour difference I[subscript DDQ] test (INDIT) for outlier identification361Power-profile driven variable voltage scaling for heterogeneous distributed real-time embedded systems369Mapping and scheduling for architecture exploration of networking SoCs376Interfacing cores with on-clip packed-switched networks382Interface design techniques for single-chip systems388CMOS digital imager design from a system-on-a-chip perspective395Extending platform-based design to network on chip systems401A method to estimate slew and delay in coupled digital circuits411Interconnect delay minimization using a novel pre-mid-post buffer strategy417Bridging fault detections for testable realizations of logic functions423Efficient RTL power estimation for large designs431Transition activity estimation for general correlated data distributions440Energy efficient scheduling for datapath synthesis446A game-theoretic approach for binding in behavioral synthesis452SPARK : a high-level synthesis framework for applying parallelizing compiler transformations461High-level synthesis of multi-process behavioral descriptions467Graph transformations for improved tree height reduction474Task graph extraction for embedded system synthesis480A new lateral SiGe-base PNM Schottky collector bipolar transistor on SOI for non-saturating VLSI logic design489Comparison of bistable circuits based on resonant-tunneling diodes493A novel dynamic threshold operation using electrically induced junction MOSFET in the deep sub-micrometer CMOS regime499A low voltage switched-capacitor current reference circuit with low dependence on process, voltage and temperature504Synthesis of programmable current mode linear analog circuit507On single/dual-rail mixed PTL/static circuits in floating-body SOI and bulk CMOS : a comparative assessment513A low power-delay product page-based address bus coding method521Minimum dynamic power CMOS circuit design by a reduced constraint set linear program527GALLOP : genetic algorithm based low power FSM synthesis by simultaneous partitioning and state assignment533A framework for energy and transient power reduction during behavioral synthesis539Low-energy BIST design for scan-based logic circuits546Genetic algorithm based approach for low power combinational circuit testing552A run-time reconfigurable system for gene-sequence searching561A run-time reconfiguration algorithm for VLSI arrays567Optimal code and data layout in embedded systems573Synthesis of real-time embedded software by timed quasi-static scheduling579SoC synthesis with automatic hardware software interface generation585
