Digital Design and Computer Architecture
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Digital Design and Computer Architecture is designed for courses that combine digital logic design with computer organization/architecture or that teach these subjects as a two-course sequence. Digital Design and Computer Architecture begins with a modern approach by rigorously covering the fundamentals of digital logic design and then introducing Hardware Description Languages (HDLs). Featuring examples of the two most widely-used HDLs, VHDL and Verilog, the first half of the text prepares the reader for what follows in the second: the design of a MIPS Processor. By the end of Digital Design and Computer Architecture, readers will be able to build their own microprocessor and will have a top-to-bottom understanding of how it works—even if they have no formal background in design or architecture beyond an introductory class. David Harris and Sarah Harris combine an engaging and humorous writing style with an updated and hands-on approach to digital design.· Unique presentation of digital logic design from the perspective of computer architecture using a real instruction set, MIPS.· Side-by-side examples of the two most prominent Hardware Design Languages—VHDL and Verilog—illustrate and compare the ways the each can be used in the design of digital systems.· Worked examples conclude each section to enhance the reader's understanding and retention of the material.· Companion Web site includes links to CAD tools for FPGA design from Synplicity and Xilinx,lecture slides, laboratory projects, and solutions to exercises.
Preface xviiFeatures xviiiOnline Supplements xixHow to Use the Software Tools in a Course xixLabs xxBugs xxiAcknowledgments xxiFrom Zero to One 3The Game Plan 3The Art of Managing Complexity 4Abstraction 4Discipline 5The Three -Y's 6The Digital Abstraction 7Number Systems 9Decimal Numbers 9Binary Numbers 9Hexadecimal Numbers 11Bytes, Nibbles, and All That Jazz 13Binary Addition 14Signed Binary Numbers 15Logic Gates 19NOT Gate 20Buffer 20AND Gate 20OR Gate 21Other Two-Input Gates 21Multiple-Input Gates 21Beneath the Digital Abstraction 22Supply Voltage 22Logic Levels 22Noise Margins 23DC Transfer Characteristics 23TheStatic Discipline 24CMOS Transistors 26Semiconductors 27Diodes 27Capacitors 28nMOS and pMOS Transistors 28CMOS NOT Gate 31Other CMOS Logic Gates 31Transmission Gates 33Pseudo-nMOS Logic 33Power Consumption 34Summary and a Look Ahead 35Exercises 37Interview Questions 48Combinational Logic Design 51Introduction 51Boolean Equations 54Terminology 54Sum-of-Products Form 54Product-of-Sums Form 56Boolean Algebra 56Axioms 57Theorems of One Variable 57Theorems of Several Variables 58The Truth Behind It All 60Simplifying Equations 61From Logic to Gates 62Multilevel Combinational Logic 65Hardware Reduction 66Bubble Pushing 67X's and Z's, Oh My 69Illegal Value: X 69Floating Value: Z 70Karnaugh Maps 71Circular Thinking 73Logic Minimization with K-Maps 73Don't Cares 77The Big Picture 78Combinational Building Blocks 79Multiplexers 79Decoders 82Timing 84Propagation and Contamination Delay 84Glitches 88Summary 91Exercises 93Interview Questions 100Sequential Logic Design 103Introduction 103Latches and Flip-Flops 103SR Latch 105D Latch 107D Flip-Plop 108Register 108Enabled Flip-Flop 109Resettable Flip-Flop 110Transistor-Level Latch and Flip-Flop Designs 110Putting It All Together 112Synchronous Logic Design 113Some Problematic Circuits 113Synchronous Sequential Circuits 114Synchronous and Asynchronous Circuits 116Finite State Machines 117FSM Design Example 117State Encodings 123Moore and Mealy Machines 126Factoring State Machines 129FSM Review 132Timing of Sequential Logic 133The Dynamic Discipline 134System Tinting 135Clock Skew 140Metastability 143Synchronizers 144Derivation of Resolution Time 146Parallelism 149Summary 153Exercises 155Interview Questions 165Hardware Description Languages 167Introduction 167Modules 167Language Origins 168Simulation and Synthesis 169Combinational Logic 171Bitwise Operators 171Comments and White Space 174Reduction Operators 174Conditional Assignment 175Internal Variables 176Precedence 178Numbers 179Z's and X's 179Bit Swizzling 182Delays 182VHDL Libraries and Types 183Structural Modeling 185Sequential Logic 190Registers 190Resettable Registers 191Enabled Registers 193Multiple Registers 194Latches 195More Combinational Logic 195Case Statements 198If Statements 199Verilog casez 201Blocking and Nonblocking Assignments 201Finite State Machines 206Parameterized Modules 211Testbenches 214Summary 218Exercises 219Interview Questions 230Digital Building Blocks 233Introduction 233Arithmetic Circuits 233Addition 233Subtraction 240Comparators 240ALU 242Shifters and Rotators 244Multiplication 246Division 247Further Reading 248Number Systems 249Fixed-Point Number Systems 249Floating-Point Number Systems 250Sequential Building Blocks 254Counters 254Shift Registers 255Memory Arrays 257Overview 257Dynamic Random Access Memory 260Static Random Access Memory 260Area and Delay 261Register Files 261Read Only Memory 262Logic Using Memory Arrays 264Memory HDL 264Logic Arrays 266Programmable Logic Array 266Field Programmable Gate Array 268Array Implementations 273Summary 274Exercises 276Interview Questions 286Architecture 289Introduction 289Assembly Language 290Instructions 290Operands: Registers, Memory, and Constants 292Machine Language 299R-type Instructions 299I-type Instructions 301J-type Instructions 302Interpreting Machine Language Code 302The Power of the Stored Program 303Programming 304Arithmetic/Logical Instructions 304Branching 308Conditional Statements 310Getting Loopy 311Arrays 314Procedure Calls 319Addressing Modes 327Lights, Camera, Action: Compiling, Assembling, and Loading 330The Memory Map 330Translating and Starting a Program 331Odds and Ends 336Pseudoinstructions 336Exceptions 337Signed and Unsigned Instructions 338Floating-Point Instructions 340Real-World Perspective: IA-32 Architecture 341IA-32 Registers 342IA-32 Operands 342Status Flags 344IA-32 Instructions 344IA-32 Instruction Encoding 346Other IA-32 Peculiarities 348The Big Picture 349Summary 349Exercises 351Interview Questions 361Microarchitecture 363Introduction 363Architectural State and Instruction Set 363Design Process 364MIPS Microarchitectures 366Performance Analysis 366Single-Cycle Processor 368Single-Cycle Datapath 368Single-Cycle Control 374More Instructions 377Performance Analysis 380Multicycle Processor 381Multicycle Datapath 382Multicycle Control 388More Instructions 395Performance Analysis 397Pipelined Processor 401Pipelined Datapath 404Pipelined Control 405Hazards 406More Instructions 418Performance Analysis 418HDL Representation 421Single-Cycle Processor 422Generic Building Blocks 426Testbench 428Exceptions 431Advanced Microarchitecture 435Deep Pipelines 435Branch Prediction 437Superscalar Processor 438Out-of-Order Processor 441Register Renaming 443Single Instruction Multiple Data 445Multithreading 446Multiprocessors 447Real-World Perspective: IA-32 Microarchitecture 447Summary 453Exercises 455Interview Questions 461Memory Systems 463Introduction 463Memory System Performance Analysis 467Caches 468What Data Is Held in the Cache? 469How Is the Data Found? 470What Data Is Replaced? 478Advanced Cache Design 479The Evolution of MIPS Caches 483Virtual Memory 484Address Translation 486The Page Table 488The Translation Lookaside Buffer 490Memory Protection 491Replacement Policies 492Multilevel Page Tables 492Memory-Mapped I/O 494Real-World Perspective: IA-32 Memory and I/O Systems 499IA-32 Cache Systems 499IA-32 Virtual Memory 501IA-32 Programmed I/O 502Summary 502Exercises 504Interview Questions 512Digital System Implementation 515Introduction 51574xx Logic 515Logic Gates 516Other Functions 516Programmable Logic 516PROMs 516PLAs 520FPGAs 521Application-Specific Integrated Circuits 523Data Sheets 523Logic Families 529Packaging and Assembly 531Transmission lines 534Matched Termination 536Open Termination 538Short Termination 539Mismatched Termination 539When to Use Transmission Line Models 542Proper Transmission Line Terminations 542Derivation of Z[subscript 0] 544Derivation of the Reflection Coefficient 545Putting It All Together 546Economics 547MIPS Instructions 551Further Reading 555Index 557
