Microprocessor Architecture: From Simple Pipelines to Chip Multiprocessors
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This book gives a comprehensive description of the architecture of microprocessors from simple in-order short pipeline designs to out-of-order superscalars. It discusses topics such asThe policies and mechanisms needed for out-of-order processing, such as register renaming, reservation stations, and reorder buffersOptimizations for high performance, such as branch predictors, instruction scheduling, and load-store speculationsDesign choices and enhancements to tolerate latency in the cache hierarchy of single and multiple processorsState-of-the-art multithreading and multiprocessing, emphasizing single-chip implementationsTopics are presented as conceptual ideas, with metrics to assess the effects on performance, if appropriate, and examples of realization. The emphasis is on how things work at a black box and algorithmic level. The author also provides sufficient detail at the register transfer level so that readers can appreciate how design features enhance performance as well as complexity.
Preface xi1 Introduction 11.1 A Quick View of Technological Advances 21.2 Performance Metrics 61.3 Performance Evaluation 121.4 Summary 221.5 Further Reading and Bibliographical Notes 23Exercises 24References 282 The Basics 292.1 Pipelining 292.2 Caches 462.3 Virtual Memory and Paging 592.4 Summary 682.5 Further Reading and Bibliographical Notes 68Exercises 69References 733 Superscalar Processors 753.1 From Scalar to Superscalar Processors 753.2 Overview of the Instruction Pipeline of the DEC Alpha 21164 783.3 Introducing Register Renaming, Reorder Buffer, and Reservation Stations 893.4 Overview of the Pentium P6 Microarchitecture 1023.5 VLIW/EPIC Processors 1113.6 Summary 1213.7 Further Reading and Bibliographical Notes 122Exercises 124References 1264 Front-End: Branch Prediction, Instruction Fetching, and Register Renaming 1294.1 Branch Prediction 130Sidebar: The DEC Alpha 21264 Branch Predictor 1574.2 Instruction Fetching 1584.3 Decoding 1644.4 Register Renaming (a Second Look) 1654.5 Summary 1704.6 Further Reading and Bibliographical Notes 170Exercises 171Programming Projects 174References 1745 Back-End: Instruction Scheduling, Memory Access Instructions, and Clusters 1775.1 Instruction Issue and Scheduling (Wakeup and Select) 1785.2 Memory-Accessing Instructions 1845.3 Back-End Optimizations 1955.4 Summary 2035.5 Further Reading and Bibliographical Notes 204Exercises 205Programming Project 206References 2066 The Cache Hierarchy 2086.1 Improving Access to L1 Caches 2096.2 Hiding Memory Latencies 2186.3 Design Issues forLarge Higher-Level Caches 2326.4 Main Memory 2456.5 Summary 2536.6 Further Reading and Bibliographical Notes 254Exercises 255Programming Projects 257References 2587 Multiprocessors 2607.1 Multiprocessor Organization 2617.2 Cache Coherence 2697.3 Synchronization 2817.4 Relaxed Memory Models 2907.5 Multimedia Instruction Set Extensions 2947.6 Summary 2967.7 Further Reading and Bibliographical Notes 297Exercises 298References 3008 Multithreading and (Chip) Multiprocessing 3038.1 Single-Processor Multithreading 3048.2 General-Purpose Multithreaded Chip Multiprocessors 3188.3 Special-Purpose Multithreaded Chip Multiprocessors 3248.4 Summary 3308.5 Further Reading and Bibliographical Notes 331Exercises 332References 3339 Current Limitations and Future Challenges 3359.1 Power and Thermal Management 3369.2 Technological Limitations: Wire Delays and Pipeline Depths 3439.3 Challenges for Chip Multiprocessors 3469.4 Summary 3489.5 Further Reading and Bibliographical Notes 349References 349Bibliography 351Index 361
