PCI System Architecture
PCI System Architecture is a detailed and comprehensive guide to the Peripheral Component Interconnect (PCI) Bus Specification, Intel's technology for fast communication between peripheral devices and the computer processor.\ This new edition has been thoroughly updated, reorganized, and expanded to cover the PCI Local Bus Specification version 2.2 and other recent developments, including the new PCI Hot-Plug Specification, changes to the PCI-to-PCI Bridge Architecture Specification,...
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PCI System Architecture is a detailed and comprehensive guide to the Peripheral Component Interconnect (PCI) Bus Specification, Intel's technology for fast communication between peripheral devices and the computer processor.This new edition has been thoroughly updated, reorganized, and expanded to cover the PCI Local Bus Specification version 2.2 and other recent developments, including the new PCI Hot-Plug Specification, changes to the PCI-to-PCI Bridge Architecture Specification, revisions to the PCI Bus Power Management Interface Specification, and the new features of the PCI BIOS Specification.This book provides clear and concise explanations of the relationship of PCI to the rest of the system and PCI fundamentals, including commands, read and write transfers, memory and I/O addressing, error handling, interrupts, and configuration transactions and registers. In addition, you will find specific information on such key topics as: Hot-Plug Specification Power management CompactPCI The 64-bit PCI Extension 66 MHz PCI Implementation Expansion ROMs PCI-to-PCI Bridge and the PCI BIOS Add-in cards and connectors Bus arbitration Reflected-wave switching Early transaction end Fast back-to-back and stepping Changes from PCI 2.1 to PCI 2.2 and changes from PCI-to-PCI Bridge Specification 1.0 to 1.1 are visibly highlighted throughout the book so that those familiar with the previous versions can quickly get a handle on new features and functions.Anyone who designs or tests hardware or software involving the PCI bus will find PCI System Architecture, Fourth Edition a valuable resource for understanding and working with this important technology.The PC System Architecture Series is a crisply written and comprehensive set of guides to the most important PC hardware standards. Each title explains from a programmer's perspective the architecture, features, and operations of systems built using one particular type of chip or hardware specification. Booknews A detailed guide to the Peripheral Component Interconnect (PCI) Bus Specification, Intel's technology for communication between peripheral devices and the computer processor. Explains the relationship of PCI to the rest of the system, and covers PCI fundamentals and changes between versions. This fourth edition has been expanded to cover the PCI Local Bus Specification version 2.2. For hardware and software design and support personnel familiar with PC and processor bus architecture. Shanley is an authority on PC system architecture. Anderson trains engineers, programmers, and technicians. Annotation c. Book News, Inc., Portland, OR (booknews.com)
\ \ Chapter 12: Early Transaction End\ ...Disconnect\ Resumption of Disconnected Transaction Is Optional\ Unlike a Retry, upon receipt of a Disconnect the master may or may not choose to rearbitrate for the bus and continue the transaction at the point of disconnection. As an example, a bridge might continue a memory read transaction past the first data phase to fill up a read-ahead buffer (i.e., a prefetch buffer) in case the originating master on the other side of the bridge wanted to read additional information. If the memory target that it's reading from disconnects from it at some point, the master would probably choose not to resume the transaction at the point of disconnection. \ Reasons Target Issues Disconnect\ Target Slow to Complete Subsequent Data Phase. Assume that the target determines that the latency to complete a data phase (except the first, which must adhere to the 16 clock rule) will be longer than eight PCI clocks. There are two cases: \ CASE 1. The target determines that it can transfer the current data item within eight clocks and also knows that the master intends to perform another data phase (the master kept FRAME# asserted when it asserted IRDY#). The target has determined that it will not be able to transfer the next data item within eight clocks after entering the next data phase. The target must assert TRDY# and STOP# thereby forcing the master to disconnect from it upon completing the transfer of the current data item. \ CASE 2. In this case, the target enters a data phase before determining that it cannot transfer a data item within eight clocks. The target must keep TRDY# deasserted and assert STOP# as soon as it determines that it cannot meet the eight clock rule. This forces the master to disconnect from the target without transferring the current data item.\ \ It should be noted that this rule was added in revision 2.1 of the specification. The target used to be permitted to take as long as it needed to transfer a data item and would then issue a Disconnect A or B (i.e., a Disconnect With Data Transfer) to the initiator. In essence, the old wording of this rule permitted a target to tie up the bus for long periods of time. This rule ensures that a slow target will not tie up the bus for extended periods of time. This subject is covered in "Subsequent Data Phase Rule" on page 84.\ Target Doesn't Support Burst Mode. If a target doesn't support burst mode and it detects that the master intends to perform a second data phase (FRAME# is still asserted when IRDY# is asserted), the target must force the master to disconnect from it. This can be handled in two ways:\ METHOD 1. The target can assert TRDY# and STOP# in the first data phase, instructing the master to transfer the first data item and then disconnect. This method is preferred over the one below because it returns the bus to the idle state more quickly so another transaction can be initiated by the next bus owner. \ METHOD 2. Alternately, the target could just assert TRDY# in the first data phase, thereby permitting the master to transfer the first data item and move into the second data phase. Upon entry into the second data phase, the target deasserts, TRDY# and asserts STOP#, instructing the master to disconnect without transferring the second data item.\ \ Memory Target Doesn't Understand Addressing Sequence. If a memory target doesn't understand the addressing sequence (see "Memory Addressing" on page 143 for more information) indicated by the initiator via AD[1:01] during the address phase, the target must disconnect from the master. It has two options:\ OPTION 1. The target can assert TRDY# and STOP# in the first data phase, instructing the master to transfer the first data item and then disconnect. This method is preferred over the one below because it returns the bus to the idle state more quickly so another transaction can be initiated by the next bus owner. \ OPTION 2. Alternately, the target could just assert TRDY# in the first data phase, thereby permitting the master to transfer the first data item and move into the second data phase. Upon entry into the second data phase, the target deasserts TRDY# and asserts STOP#, instructing the master to disconnect without transferring the second data item.\ \ This forces the initiator to fragment a burst transaction into single data phase transactions that the target can handle. The initiator may be using an AD[1:01] pattern defined in a later revision of the specification than the target was designed to.\ Transfer Crosses Over Target's Address Boundary. If a target determines during the current data phase that the initiator intends to perform another data phase (FRAME# is still asserted) and that the current data item is the last within its address boundaries, the target must disconnect from the master. It has two options:\ OPTION 1. The target can assert TRDY# and STOP# in the current data phase, instructing the master to transfer the current data item and then disconnect. This method is preferred over the one below because it returns the bus to the idle state more quickly so another transaction can be initiated by the next bus owner. \ OPTION 2. Alternately, the target could just assert TRDY# in the current data phase, thereby permitting the master to transfer the first data item and move into the next data phase. Upon entry into the next data phase, the target deasserts TRDY# and asserts STOP#, instructing the master to disconnect without transferring the next data item.\ \ The master then waits two PCI clocks and reasserts its REQ# to request ownership of the bus again. When it has re-acquired bus ownership, it resumes its transaction using the next dword address. This gives an opportunity to another target that implements the next sequential dword address to claim the transaction, thereby permitting the transfer to continue across target boundaries...
About This BookCh. 1Intro To PCICh. 2Intro to PCI Bus OperationCh. 3Intro to Reflected-Wave SwitchingCh. 4The Signal GroupsCh. 5PCI Bus ArbitrationCh. 6Master and Target LatencyCh. 7The CommandsCh. 8Read TransfersCh. 9Write TransfersCh. 10Memory and IO AddressingCh. 11Fast Back-to-Back & SteppingCh. 12Early Transaction EndCh. 13Error Detection and HandlingCh. 14InterruptsCh. 15The 64-bit PCI ExtensionCh. 1666MHz PCI ImplementationCh. 17Intro to Configuration Address SpaceCh. 18Configuration TransactionsCh. 19Configuration RegistersCh. 20Expansion ROMsCh. 21Add-in Cards and ConnectorsCh. 22Hot-Plug PCICh. 23Power ManagementCh. 24PCI-to-PCI BridgeCh. 25Transaction Ordering & DeadlocksCh. 26The PCI BIOSCh. 27LockingCh. 28CompactPCI and PMCApp. A - Glossary of Terms
\ BooknewsA detailed guide to the Peripheral Component Interconnect (PCI) Bus Specification, Intel's technology for communication between peripheral devices and the computer processor. Explains the relationship of PCI to the rest of the system, and covers PCI fundamentals and changes between versions. This fourth edition has been expanded to cover the PCI Local Bus Specification version 2.2. For hardware and software design and support personnel familiar with PC and processor bus architecture. Shanley is an authority on PC system architecture. Anderson trains engineers, programmers, and technicians. Annotation c. Book News, Inc., Portland, OR (booknews.com)\ \
