CMOS VLSI Design: A Circuits and Systems Perspective

Chapter 1 Introduction1.1 A Brief History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2 Preview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61.3 MOS Transistors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61.4 CMOS Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91.4.1 The Inverter 91.4.2 The NAND Gate 91.4.3 CMOS Logic Gates 91.4.4 The NOR Gate 111.4.5 Compound Gates 111.4.6 Pass Transistors and Transmission Gates 121.4.7 Tristates 141.4.8 Multiplexers 151.4.9 Sequential Circuits 161.5 CMOS Fabrication and Layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191.5.1 Inverter Cross-Section 191.5.2 Fabrication Process 201.5.3 Layout Design Rules 241.5.4 Gate Layouts 271.5.5 Stick Diagrams 281.6 Design Partitioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291.6.1 Design Abstractions 301.6.2 Structured Design 311.6.3 Behavioral, Structural, and Physical Domains 311.7 Example: A Simple MIPS Microprocessor. . . . . . . . . . . . . . . . . . . . . . . . . . . 331.7.1 MIPS Architecture 331.7.2 Multicycle MIPS Microarchitectures 341.8 Logic Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381.8.1 Top-Level Interfaces 381.8.2 Block Diagrams 381.8.3 Hierarchy 401.8.4 Hardware Description Languages 401.9 Circuit Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421.10 Physical Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 451.10.1 Floorplanning 451.10.2 Standard Cells 481.10.3 Pitch Matching 501.10.4 Slice Plans 501.10.5 Arrays 511.10.6 Area Estimation 511.11 Design Verification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531.12 Fabrication, Packaging, and Testing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54Summary and a Look Ahead 55Exercises 57Chapter 2 MOS Transistor Theory2.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 612.2 Long-Channel I-V Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 642.3 C-V Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 682.3.1 Simple MOS Capacitance Models 682.3.2 Detailed MOS Gate Capacitance Model 702.3.3 Detailed MOS Diffusion Capacitance Model 722.4 Nonideal I-V Effects. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 742.4.1 Mobility Degradation and Velocity Saturation 752.4.2 Channel Length Modulation 782.4.3 Threshold Voltage Effects 792.4.4 Leakage 802.4.5 Temperature Dependence 852.4.6 Geometry Dependence 862.4.7 Summary 862.5 DC Transfer Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 872.5.1 Static CMOS Inverter DC Characteristics 882.5.2 Beta Ratio Effects 902.5.3 Noise Margin 912.5.4 Pass Transistor DC Characteristics 922.6 Pitfalls and Fallacies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93Summary 94Exercises 95Chapter 3 CMOS Processing Technology3.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 993.2 CMOS Technologies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1003.2.1 Wafer Formation 1003.2.2 Photolithography 1013.2.3 Well and Channel Formation 1033.2.4 Silicon Dioxide (SiO2) 1053.2.5 Isolation 1063.2.6 Gate Oxide 1073.2.7 Gate and Source/Drain Formations 1083.2.8 Contacts and Metallization 1103.2.9 Passivation 1123.2.10 Metrology 1123.3 Layout Design Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1133.3.1 Design Rule Background 1133.3.2 Scribe Line and Other Structures 1163.3.3 MOSIS Scalable CMOS Design Rules 1173.3.4 Micron Design Rules 1183.4 CMOS Process Enhancements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1193.4.1 Transistors 1193.4.2 Interconnect 1223.4.3 Circuit Elements 1243.4.4 Beyond Conventional CMOS 1293.5 Technology-Related CAD Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1303.5.1 Design Rule Checking (DRC) 1313.5.2 Circuit Extraction 1323.6 Manufacturing Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1333.6.1 Antenna Rules 1333.6.2 Layer Density Rules 1343.6.3 Resolution Enhancement Rules 1343.6.4 Metal Slotting Rules 1353.6.5 Yield Enhancement Guidelines 1353.7 Pitfalls and Fallacies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1363.8 Historical Perspective . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137Summary 139Exercises 139Chapter 4 Delay4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1414.1.1 Definitions 1414.1.2 Timing Optimization 1424.2 Transient Response . . . . . . . . . . . . . . . . . . . . . . . 1434.3 RC Delay Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1464.3.1 Effective Resistance 1464.3.2 Gate and Diffusion Capacitance 1474.3.3 Equivalent RC Circuits 1474.3.4 Transient Response 1484.3.5 Elmore Delay 1504.3.6 Layout Dependence of Capacitance 1534.3.7 Determining Effective Resistance 1544.4 Linear Delay Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1554.4.1 Logical Effort 1564.4.2 Parasitic Delay 1564.4.3 Delay in a Logic Gate 1584.4.4 Drive 1594.4.5 Extracting Logical Effort from Datasheets 1594.4.6 Limitations to the Linear Delay Model 1604.5 Logical Effort of Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1634.5.1 Delay in Multistage Logic Networks 1634.5.2 Choosing the Best Number of Stages 1664.5.3 Example 1684.5.4 Summary and Observations 1694.5.5 Limitations of Logical Effort 1714.5.6 Iterative Solutions for Sizing 1714.6 Timing Analysis Delay Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1734.6.1 Slope-Based Linear Model 1734.6.2 Nonlinear Delay Model 1744.6.3 Current Source Model 1744.7 Pitfalls and Fallacies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1744.8 Historical Perspective . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175Summary 176Exercises 176Chapter 5 Power5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1815.1.1 Definitions 1825.1.2 Examples 1825.1.3 Sources of Power Dissipation 1845.2 Dynamic Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1855.2.1 Activity Factor 1865.2.2 Capacitance 1885.2.3 Voltage 1905.2.4 Frequency 1925.2.5 Short-Circuit Current 1935.2.6 Resonant Circuits 1935.3 Static Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1945.3.1 Static Power Sources 1945.3.2 Power Gating 1975.3.3 Multiple Threshold Voltages and Oxide Thicknesses 195.3.4 Variable Threshold Voltages 1995.3.5 Input Vector Control 2005.4 Energy-Delay Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2005.4.1 Minimum Energy 2005.4.2 Minimum Energy-Delay Product 2035.4.3 Minimum Energy Under a Delay Constraint 2035.5 Low Power Architectures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2045.5.1 Microarchitecture 2045.5.2 Parallelism and Pipelining 2045.5.3 Power Management Modes 2055.6 Pitfalls and Fallacies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2065.7 Historical Perspective . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207Summary 209Exercises 209Chapter 6 Interconnect6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2116.1.1 Wire Geometry 2116.1.2 Example: Intel Metal Stacks 2126.2 Interconnect Modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2136.2.1 Resistance 2146.2.2 Capacitance 2156.2.3 Inductance 2186.2.4 Skin Effect 2196.2.5 Temperature Dependence 2206.3 Interconnect Impact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2206.3.1 Delay 2206.3.2 Energy 2226.3.3 Crosstalk 2226.3.4 Inductive Effects 2246.3.5 An Aside on Effective Resistance and Elmore Delay 2276.4 Interconnect Engineering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2296.4.1 Width, Spacing, and Layer 2296.4.2 Repeaters 2306.4.3 Crosstalk Control 2326.4.4 Low-Swing Signaling 2346.4.5 Regenerators 2366.5 Logical Effort with Wires . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2366.6 Pitfalls and Fallacies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237Summary 238Exercises 238Chapter 7 Robustness7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2417.2 Variability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2417.2.1 Supply Voltage 2427.2.2 Temperature 2427.2.3 Process Variation 2437.2.4 Design Corners 2447.3 Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2467.3.1 Reliability Terminology 2467.3.2 Oxide Wearout 2477.3.3 Interconnect Wearout 2497.3.4 Soft Errors 2517.3.5 Overvoltage Failure 2527.3.6 Latchup 2537.4 Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2547.4.1 Transistor Scaling 2557.4.2 Interconnect Scaling 2577.4.3 International Technology Roadmap for Semiconductors 2587.4.4 Impacts on Design 2597.5 Statistical Analysis of Variability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2637.5.1 Properties of Random Variables 2637.5.2 Variation Sources 2667.5.3 Variation Impacts 2697.6 Variation-Tolerant Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2747.6.1 Adaptive Control 2757.6.2 Fault Tolerance 2757.7 Pitfalls and Fallacies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2777.8 Historical Perspective . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278Summary 284Exercises 284Chapter 8 Circuit Simulation8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2878.2 A SPICE Tutorial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2888.2.1 Sources and Passive Components 2888.2.2 Transistor DC Analysis 2928.2.3 Inverter Transient Analysis 2928.2.4 Subcircuits and Measurement 2948.2.5 Optimization 2968.2.6 Other HSPICE Commands 2988.3 Device Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2988.3.1 Level 1 Models 2998.3.2 Level 2 and 3 Models 3008.3.3 BSIM Models 3008.3.4 Diffusion Capacitance Models 3008.3.5 Design Corners 3028.4 Device Characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3038.4.1 I-V Characteristics 3038.4.2 Threshold Voltage 3068.4.3 Gate Capacitance 3088.4.4 Parasitic Capacitance 3088.4.5 Effective Resistance 3108.4.6 Comparison of Processes 3118.4.7 Process and Environmental Sensitivity 3138.5 Circuit Characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3138.5.1 Path Simulations 3138.5.2 DC Transfer Characteristics 3158.5.3 Logical Effort 3158.5.4 Power and Energy 3188.5.5 Simulating Mismatches 3198.5.6 Monte Carlo Simulation 3198.6 Interconnect Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3198.7 Pitfalls and Fallacies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322Summary 324Exercises 324Chapter 9 Combinational Circuit Design9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3279.2 Circuit Families . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3289.2.1 Static CMOS 3299.2.2 Ratioed Circuits 3349.2.3 Cascode Voltage Switch Logic 3399.2.4 Dynamic Circuits 3399.2.5 Pass-Transistor Circuits 3499.3 Circuit Pitfalls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3549.3.1 Threshold Drops 3559.3.2 Ratio Failures 3559.3.3 Leakage 3569.3.4 Charge Sharing 3569.3.5 Power Supply Noise 3569.3.6 Hot Spots 3579.3.7 Minority Carrier Injection 3579.3.8 Back-Gate Coupling 3589.3.9 Diffusion Input Noise Sensitivity 3589.3.10 Process Sensitivity 3589.3.11 Example: Domino Noise Budgets 3599.4 More Circuit Families . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3609.5 Silicon-On-Insulator Circuit Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3609.5.1 Floating Body Voltage 3619.5.2 SOI Advantages 3629.5.3 SOI Disadvantages 3629.5.4 Implications for Circuit Styles 3639.5.5 Summary 3649.6 Subthreshold Circuit Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3649.6.1 Sizing 3659.6.2 Gate Selection 3659.7 Pitfalls and Fallacies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3669.8 Historical Perspective . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367Summary 369Exercises 370Chapter 10 Sequential Circuit Design10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37510.2 Sequencing Static Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37610.2.1 Sequencing Methods 37610.2.2 Max-Delay Constraints 37910.2.3 Min-Delay Constraints 38310.2.4 Time Borrowing 38610.2.5 Clock Skew 38910.3 Circuit Design of Latches and Flip-Flops . . . . . . . . . . . . . . . . . . . . . . . . . . . 39110.3.1 Conventional CMOS Latches 39210.3.2 Conventional CMOS Flip-Flops 39310.3.3 Pulsed Latches 39510.3.4 Resettable Latches and Flip-Flops 39610.3.5 Enabled Latches and Flip-Flops 39710.3.6 Incorporating Logic into Latches 39810.3.7 Klass Semidynamic Flip-Flop (SDFF) 39910.3.8 Differential Flip-Flops 39910.3.9 Dual Edge-Triggered Flip-Flops 40010.3.10 Radiation-Hardened Flip-Flops 40110.3.11 True Single-Phase-Clock (TSPC) Latches and Flip-Flops 40210.4 Static Sequencing Element Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . 40210.4.1 Choice of Elements 40310.4.2 Characterizing Sequencing Element Delays 40510.4.3 State Retention Registers 40810.4.4 Level-Converter Flip-Flops 40810.4.5 Design Margin and Adaptive Sequential Elements 40910.4.6 Two-Phase Timing Types 41110.5 Sequencing Dynamic Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41110.6 Synchronizers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41110.6.1 Metastability 41210.6.2 A Simple Synchronizer 41510.6.3 Communicating Between Asynchronous Clock Domains 41610.6.4 Common Synchronizer Mistakes 41710.6.5 Arbiters 41910.6.6 Degrees of Synchrony 41910.7 Wave Pipelining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42010.8 Pitfalls and Fallacies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42210.9 Case Study: Pentium 4 and Itanium 2 Sequencing Methodologies . . . . . 423Summary 423Exercises 425Chapter 11 Datapath Subsystems11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42911.2 Addition/Subtraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42911.2.1 Single-Bit Addition 43011.2.2 Carry-Propagate Addition 43411.2.3 Subtraction 45811.2.4 Multiple-Input Addition 45811.2.5 Flagged Prefix Adders 45911.3 One/Zero Detectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46111.4 Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46211.4.1 Magnitude Comparator 46211.4.2 Equality Comparator 46211.4.3 K = A + B Comparator 46311.5 Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46311.5.1 Binary Counters 46411.5.2 Fast Binary Counters 46511.5.3 Ring and Johnson Counters 46611.5.4 Linear-Feedback Shift Registers 46611.6 Boolean Logical Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46811.7 Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46811.7.1 Parity 46811.7.2 Error-Correcting Codes 46811.7.3 Gray Codes 47011.7.4 XOR/XNOR Circuit Forms 47111.8 Shifters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47211.8.1 Funnel Shifter 47311.8.2 Barrel Shifter 47511.8.3 Alternative Shift Functions 47611.9 Multiplication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47611.9.1 Unsigned Array Multiplication 47811.9.2 Two’s Complement Array Multiplication 47911.9.3 Booth Encoding 48011.9.4 Column Addition 48511.9.5 Final Addition 48911.9.6 Fused Multiply-Add 49011.9.7 Serial Multiplication 49011.9.8 Summary 49011.10 Parallel-Prefix Computations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49111.11 Pitfalls and Fallacies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493Summary 494Exercises 494Chapter 12 Array Subsystems12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49712.2 SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49812.2.1 SRAM Cells 49912.2.2 Row Circuitry 50612.2.3 Column Circuitry 51012.2.4 Multi-Ported SRAM and Register Files 51412.2.5 Large SRAMs 51512.2.6 Low-Power SRAMs 51712.2.7 Area, Delay, and Power of RAMs and Register Files 52012.3 DRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52212.3.1 Subarray Architectures 52312.3.2 Column Circuitry 52512.3.3 Embedded DRAM 52612.4 Read-Only Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52712.4.1 Programmable ROMs 52912.4.2 NAND ROMs 53012.4.3 Flash 53112.5 Serial Access Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53312.5.1 Shift Registers 53312.5.2 Queues (FIFO, LIFO) 53312.6 Content-Addressable Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53512.7 Programmable Logic Arrays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53712.8 Robust Memory Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54112.8.1 Redundancy 54112.8.2 Error Correcting Codes (ECC) 54312.8.3 Radiation Hardening 54312.9 Historical Perspective . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 544Summary 545Exercises 546Chapter 13 Special-Purpose Subsystems13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54913.2 Packaging and Cooling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54913.2.1 Package Options 54913.2.2 Chip-to-Package Connections 55113.2.3 Package Parasitics 55213.2.4 Heat Dissipation 55213.2.5 Temperature Sensors 55313.3 Power Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55513.3.1 On-Chip Power Distribution Network 55613.3.2 IR Drops 55713.3.3 L di/dt Noise 55813.3.4 On-Chip Bypass Capacitance 55913.3.5 Power Network Modeling 56013.3.6 Power Supply Filtering 56413.3.7 Charge Pumps 56413.3.8 Substrate Noise 56513.3.9 Energy Scavenging 56513.4 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56613.4.1 Definitions 56613.4.2 Clock System Architecture 56813.4.3 Global Clock Generation 56913.4.4 Global Clock Distribution 57113.4.5 Local Clock Gaters 57513.4.6 Clock Skew Budgets 57713.4.7 Adaptive Deskewing 57913.5 PLLs and DLLs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58013.5.1 PLLs 58013.5.2 DLLs 58713.5.3 Pitfalls 58913.6 I/0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59013.6.1 Basic I/O Pad Circuits 59113.6.2 Electrostatic Discharge Protection 59313.6.3 Example: MOSIS I/O Pads 59413.6.4 Mixed-Voltage I/O 59613.7 High-Speed Links . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59713.7.1 High-Speed I/O Channels 59713.7.2 Channel Noise and Interference 60013.7.3 High-Speed Transmitters and Receivers 60113.7.4 Synchronous Data Transmission 60613.7.5 Clock Recovery in Source-Synchronous Systems 60613.7.6 Clock Recovery in Mesochronous Systems 60813.7.7 Clock Recovery in Pleisochronous Systems 61013.8 Random Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61013.8.1 True Random Number Generators 61013.8.2 Chip Identification 61113.9 Pitfalls and Fallacies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 612Summary 613Exercises 614Chapter 14 Design Methodology and Tools14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61514.2 Structured Design Strategies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61714.2.1 A Software Radio–A System Example 61814.2.2 Hierarchy 62014.2.3 Regularity 62314.2.4 Modularity 62514.2.5 Locality 62614.2.6 Summary 62714.3 Design Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62714.3.1 Microprocessor/DSP 62714.3.2 Programmable Logic 62814.3.3 Gate Array and Sea of Gates Design 63114.3.4 Cell-Based Design 63214.3.5 Full Custom Design 63414.3.6 Platform-Based Design–System on a Chip 63514.3.7 Summary 63614.4 Design Flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63614.4.1 Behavioral Synthesis Design Flow (ASIC Design Flow) 63714.4.2 Automated Layout Generation 64114.4.3 Mixed-Signal or Custom-Design Flow 64514.5 Design Economics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64614.5.1 Non-Recurring Engineering Costs (NREs) 64714.5.2 Recurring Costs 64914.5.3 Fixed Costs 65014.5.4 Schedule 65114.5.5 Personpower 65314.5.6 Project Management 65314.5.7 Design Reuse 65414.6 Data Sheets and Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65514.6.1 The Summary 65514.6.2 Pinout 65514.6.3 Description of Operation 65514.6.4 DC Specifications 65514.6.5 AC Specifications 65614.6.6 Package Diagram 65614.6.7 Principles of Operation Manual 65614.6.8 User Manual 65614.7 CMOS Physical Design Styles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65614.8 Pitfalls and Fallacies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657Exercises 657Chapter 15 Testing, Debugging, and Verification15.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65915.1.1 Logic Verification 66015.1.2 Debugging 66215.1.3 Manufacturing Tests 66415.2 Testers, Test Fixtures, and Test Programs . . . . . . . . . . . . . . . . . . . . . . . . . . 66615.2.1 Testers and Test Fixtures 66615.2.2 Test Programs 66815.2.3 Handlers 66915.3 Logic Verification Principles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67015.3.1 Test Vectors 67015.3.2 Testbenches and Harnesses 67115.3.3 Regression Testing 67115.3.4 Version Control 67215.3.5 Bug Tracking 67315.4 Silicon Debug Principles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67315.5 Manufacturing Test Principles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67615.5.1 Fault Models 67715.5.2 Observability 67915.5.3 Controllability 67915.5.4 Repeatability 67915.5.5 Survivability 67915.5.6 Fault Coverage 68015.5.7 Automatic Test Pattern Generation (ATPG) 68015.5.8 Delay Fault Testing 68015.6 Design for Testability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68115.6.1 Ad Hoc Testing 68115.6.2 Scan Design 68215.6.3 Built-In Self-Test (BIST) 68415.6.4 IDDQ Testing 68715.6.5 Design for Manufacturability 68715.7 Boundary Scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68815.8 Testing in a University Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68915.9 Pitfalls and Fallacies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 690Summary 697Exercises 697Appendix A Hardware Description LanguagesA.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 699A.1.1 Modules 700A.1.2 Simulation and Synthesis 701A.2 Combinational Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 702A.2.1 Bitwise Operators 702A.2.2 Comments and White Space 703A.2.3 Reduction Operators 703A.2.4 Conditional Assignment 704A.2.5 Internal Variables 706A.2.6 Precedence and Other Operators 708A.2.7 Numbers 708A.2.8 Zs and Xs 709A.2.9 Bit Swizzling 711A.2.10 Delays 712A.3 Structural Modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 713A.4 Sequential Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 717A.4.1 Registers 717A.4.2 Resettable Registers 718A.4.3 Enabled Registers 719A.4.4 Multiple Registers 720A.4.5 Latches 721A.4.6 Counters 722A.4.7 Shift Registers 724A.5 Combinational Logic with Always / Process Statements . . . . . . . . . . . . . . 724A.5.1 Case Statements 726A.5.2 If Statements 729A.5.3 SystemVerilog Casez 731A.5.4 Blocking and Nonblocking Assignments 731A.6 Finite State Machines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 735A.6.1 FSM Example 735A.6.2 State Enumeration 736A.6.3 FSM with Inputs 738A.7 Type Idiosyncracies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 740A.8 Parameterized Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 742A.9 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 745A.9.1 RAM 745A.9.2 Multiported Register Files 747A.9.3 ROM 748A.10 Testbenches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 749A.11 SystemVerilog Netlists . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 754A.12 Example: MIPS Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 755A.12.1 Testbench 756A.12.2 SystemVerilog 757A.12.3 VHDL 766Exercises 776References 785Index 817Credits 838