Modeling Microprocessor Performance
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Modeling Microprocessor Performance focuses on the development of a design and evaluation tool, named RIPE (Rensselaer Interconnect Performance Estimator). This tool analyzes the impact on wireability, clock frequency, power dissipation, and the reliability of single chip CMOS microprocessors as a function of interconnect, device, circuit, design and architectural parameters. It can accurately predict the overall performance of existing microprocessor systems. For the three major microprocessor architectures, DEC, PowerPC and Intel, the results have shown agreement within 10% on key parameters. The models cover a broad range of issues that relate to the implementation and performance of single chip CMOS microprocessors. The book contains a detailed discussion of the various models and the underlying assumptions based on actual design practices. As such, RIPE and its models provide an insightful tool into single chip microprocessor design and its performance aspects. At the same time, it provides design and process engineers with the capability to model, evaluate, compare and optimize single chip microprocessor systems using advanced technology and design techniques at an early design stage without costly and time consuming implementation. RIPE and its models demonstrate the factors which must be considered when estimating tradeoffs in device and interconnect technology and architecture design on microprocessor performance. Booknews Presents the development of a design and evaluation tool named RIPE (Rensselaer Interconnect Performance Estimator), which design and process engineers can use for modeling at an early stage of microprocessor design. The program analyzes the impact on size, wireability, clock frequency, power dissipation and reliability of single chip CMOS microprocessors as a function of interconnect, device, circuit, design and architectural parameters. The book describes various models and underlying assumptions used in RIPE version 3.0, and offers a website to examine the program. The content is based entirely on doctoral work done at Rensselaer Polytechnic Institute, Troy, NY. Annotation c. by Book News, Inc., Portland, Or.
PrefaceAcknowledgements1Introduction12System Level Representation173Interconnect Parameters274Transistor Count and Area Models535System Wireability916Device Parameters1257Cycle Time Estimation Model1358System Power Dissipation1559Microprocessor Performance Evaluation175Index193
