Processor Architecture: From Dataflow to Superscalar and Beyond
A survey of architectural mechanisms and implementation techniques for exploiting fine- and coarse-grained parallelism within microprocessors. Beginning with a review of past techniques, the monograph provides a comprehensive account of state-of-the-art techniques used in microprocessors, covering both the concepts involved and implementations in sample processors. The whole is rounded off with a thorough review of the research techniques that will lead to future microprocessors. XXXXXXX...
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This monograph surveys architectural mechanisms and implementation techniques for exploiting fine-grained and coarse-grained parallelism within microprocessors. It starts with a review of past techniques, continues with a comprehensive account of state-of-the-art techniques used in microprocessors that covers both the concepts involved and implementations in sample processors, and ends with a thorough review of the research techniques that will lead to future microprocessors.
1Basic Pipelining and Simple RISC Processors12Dataflow Processors553CISC Processors994Multiple-Issue Processors1235Future Processors to use Fine-Grain Parallelism2216Future Processors to use Coarse-Grain Parallelism2477Processor-in-Memory, Reconfigurable, and Asynchronous Processors299Acronyms335Glossary343References361Index379
