High Speed CMOS Design Styles
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High Speed CMOS Design Styles is written for the graduate-level student or practicing engineer who is primarily interested in circuit design. It is intended to provide practical reference, or `horse-sense', to mechanisms typically described with a more academic slant. This book is organized so that it can be used as a textbook or as a reference book. High Speed CMOS Design Styles provides a survey of design styles in use in industry, specifically in the high speed microprocessor design community. Logic circuit structures, I/O and interface, clocking, and timing schemes are reviewed and described. Characteristics, sensitivities and idiosyncrasies of each are highlighted. High Speed CMOS Design Styles also pulls together and explains contributors to performance variability that are associated with process, applications conditions and design. Rules of thumb and practical references are offered. Each of the general circuit families is then analyzed for its sensitivity and response to this variability. High Speed CMOS Design Styles is an excellent source of ideas and a compilation of observations that highlight how different approaches trade off critical parameters in design and process space. Booknews Seven authors with IBM Microelectronics provide a more pragmatic than academic survey for practicing engineers and graduate students in design styles used in the high speed microprocessor design industry. In keeping with the practical approach, the discussion rests on a foundation of the general circuit families, basic process-related design considerations, and rules of thumb for dealing with such matters as process-driven performance variation in quarter-micron CMOS. Diagram-studded chapters cover: process variability, non-clocked and clocked logic styles, circuit design margin and design variability, latching strategies, interface techniques, clocking styles, slack borrowing and time stealing, and future technology to enable circuit configurations not currently feasible. Annotation c. by Book News, Inc., Portland, Or.
PrefaceCh. 1Process Variability1Ch. 2Non-Clocked Logic Styles51Ch. 3Clocked Logic Styles91Ch. 4Circuit Design Margin and Design Variability133Ch. 5Latching Strategies175Ch. 6Interface Techniques207Ch. 7Clocking Styles247Ch. 8Slack Borrowing and Time Stealing285Ch. 9Future Technology335Index347
