Hot-Carrier Reliability Of Mos Vlsi Circuits
This volume addresses the issues related to hot-carrier reliability of MOS VLSI circuits, ranging from device physics to circuit design guidelines. It presents a unified view of the physical mechanisms involved in hot-carrier induced device degradation, the prevalent models for these mechanisms, and simulation methods for estimating hot-carrier effects in the circuit environment. The newly emerging approaches to the VLSI design-for-reliability and rule-based reliability diagnosis are also...
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This volume addresses the issues related to hot-carrier reliability of MOS VLSI circuits, ranging from device physics to circuit design guidelines. It presents a unified view of the physical mechanisms involved in hot-carrier induced device degradation, the prevalent models for these mechanisms, and simulation methods for estimating hot-carrier effects in the circuit environment. The newly emerging approaches to the VLSI design-for-reliability and rule-based reliability diagnosis are also discussed in detail. Hot-Carrier Reliability of MOS VLSI Circuits is primarily for use by engineers and scientists who study device and circuit-level reliability in VLSI systems and develop practical reliability measures and models. VLSI designers will benefit from this book since it offers a comprehensive overview of the interacting mechanisms that influence hot-carrier reliability, and also provides useful guidelines for reliable VLSI design. This volume can be used as an advanced textbook or reference for a graduate-level course on VLSI reliability.
PrefaceAcknowledgements1Introduction11.1The Concept of IC Reliability11.2Design-for-Reliability41.3VLSI Reliability Problems61.4Gradual Degradation versus Catastrophic Failures71.5Hot-Carrier Effects92Oxide Degradation Mechanisms in MOS Transistors152.2MOS Transistor : A Qualitative View162.3The Nature of Gate Oxide Damage in MOSFETs192.4Injection of Hot Carriers into Gate Oxide212.5Oxide Traps and Charge Trapping312.6Interface Trap Generation342.7Bias Dependence of Degradation Mechanisms362.8Degradation under Dynamic Operating Conditions392.9Effects of Hot-Carrier Damage on Device Characteristics432.10Hot-Carrier Induced Degradation of pMOS Transistors473Modeling of Degradation Mechanisms553.2Quasi-Elastic Scattering Current Model563.3Charge (Electron) Trapping Model643.4Impact Ionization Current Model663.5Interface Trap Generation Model673.6Trap Generation under Dynamic Operating Conditions714Modeling of Damaged MOSFETs774.2Representation of Hot-Carrier Induced Oxide Damage784.3Two-Dimensional Modeling of Damaged MOSFETs804.4Empirical One-Dimensional Modeling834.5An Analytical Damaged MOSFET Model894.6Consideration of Channel Velocity Limitations1014.7Pseudo Two-Dimensional Modeling of Damaged MOSFETs1034.8Table-Based Modeling Approaches1045Transistor-Level Simulation for Circuit Reliability1115.2Review of Circuit Reliability Simulation Tools1125.3Circuit Reliability Simulation Using iSMILE : A Case Study1195.4Circuit Simulation Examples1245.5Evaluation of the Simulation Algorithm1335.6Identification of Critical Devices1366Fast Timing Simulation for Circuit Reliability1436.2ILLIADS-R : A Fast Timing and Reliability Simulator1446.3Fast Dynamic Reliability Simulation1486.4Circuit Simulation Examples with ILLIADS-R1556.5iDSIM2 : Hierarchical Circuit Reliability Simulation1597Macromodeling of Hot-Carrier Induced Degradation in MOS Circuits1657.2Macromodel Development : Starting Assumptions1667.3Degradation Macromodel for CMOS Inverters1677.4Degradation Macromodel for nMOS Pass Gates1737.5Application of the Macromodel to Inverter Chain Circuits1797.6Application of the Macromodel to CMOS Logic Circuits1868Circuit Design for Reliability1918.2Device-Level Measures1938.3Circuit-Level Measures1998.4Rule-Based Diagnosis of Circuit Reliability203Index209
