VLSI Circuit Design Methodology Demystified: A Conceptual Taxonomy
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An accessible, intuitive resource to common—and not-so-common—questions and answers about very large-scale integrated (VLSI) circuit designThe widespread acceptance of sophisticated electronic devices and the growing challenges of a more technically oriented future have created an unprecedented demand for very large-scale integrated (VLSI) circuits. Meeting this crucial need requires advances in material science and processing equipment along with the ability to use the computer more effectively to aid in the design process. More importantly, it also requires a significant number of qualified professionals to work in this exciting field. Unfortunately, due to its complexity and dynamic nature, the topic of VLSI circuit design methodology is not widely taught in universities nor is it well understood by many engineers. Now, VLSI Circuit Design Methodology Demystified takes the guesswork out of this important topic by presenting readers with a succinct and accessible treatment of how a complex chip is developed, from concept to silicon. Uniquely organized in a question-and-answer format, the book builds on information in the order of chip development: market research/product definition, system design, logic design, logic verification, logic synthesis, Place & Route, and physical verification. A wealth of important questions are addressed, including:What are the requirements of a successful chip design?What are the major approaches of today's VLSI circuit design practices?What are the major process steps in building MOSFET transistors?What is the role of functional verification in the IC design process?What are the two major aspects of ASIC design flow?What is Hardware Description Language (HDL)?What is the most commonly used model in VLSI circuit testing?What are the qualities of a good IC implementation designer?The answers to these questions and many more provide the framework for understanding the key concepts involved in the VLSI chip development process, giving readers a solid foundation for further advancement in the field. Written by an industry expert, the book uses up-to-date, real-world design examples to demonstrate to readers how to become better engineers through a practical approach of diagnosing and attacking problems. Ideal as a resource for electrical engineers specializing in integrated circuit design in the semiconductor industry, this book is also suitable as a supplementary text for students enrolled in advanced VLSI courses.
Foreword Richard Templeton xiForeword Hans Stork xiiiPreface xvAcknowledgments xviiThe Big Picture 1What is a chip? 1What are the requirements of a successful chip design? 3What are the challenges in today's very deep submicron (VDSM), multimillion gate designs? 4What major process technologies are used in today's design environment? 5What are the goals of new chip design? 8What are the major approaches of today's very large scale integration (VLSI) circuit design practices? 9What is standard cell-based, application-specific integrated circuit (ASIC) design methodology? 11What is the system-on-chip (SoC) approach? 12What are the driving forces behind the SoC trend? 15What are the major tasks in developing a SoC chip from concept to silicon? 15What are the major costs of developing a chip? 16The Basics of the CMOS Process and Devices 17What are the major process steps in building MOSFET transistors? 17What are the two types of MOSFET transistors? 19What are base layers and metal layers? 20What are wafers anddies? 24What is semiconductor lithography? 28What is a package? 33The Challenges in VLSI Circuit Design 41What is the role of functional verification in the IC design process? 41What are some of the design integrity issues? 44What is design for testability? 46Why is reducing the chip's power consumption so important? 48What are some of the challenges in chip packaging? 49What are the advantages of design reuse? 50What is hardware/software co-design? 51Why is the clock so important? 54What is the leakage current problem? 57What is design for manufacturability? 60What is chip reliability? 62What is analog integration in the digital environment? 65What is the role of EDA tools in IC design? 67What is the role of the embedded processor in the SoC environment? 69Cell-Based ASIC Design Methodology 73What are the major tasks and personnel required in a chip design project? 73What are the major steps in ASIC chip construction? 74What is the ASIC design flow? 75What are the two major aspects of ASIC design flow? 77What are the characteristics of good design flow? 80What is the role of market research in an ASIC project? 81What is the optimal solution of an ASIC project? 82What is system-level study of a project? 84What are the approaches for verifying design at the system level? 85What is register-transfer-level (RTL) system-level description? 86What are methods of verifying design at the register-transfer-level? 87What is a test bench? 88What is code coverage? 89What is functional coverage? 89What is bug rate convergence? 90What is design planning? 91What are hard macro and soft macro? 92What is hardware description language (HDL)? 92What is register-transfer-level (RTL) description of hardware? 93What is standard cell? What are the differences among standard cell, gate-array, and sea-of-gate approaches? 94What is an ASIC library? 103What is logic synthesis? 105What are the optimization targets of logic synthesis? 106What is schematic or netlist? 107What is the gate count of a design? 111What is the purpose of test insertion during logic synthesis? 111What is the most commonly used model in VLSI circuit testing? 112What are controllability and observability in a digital circuit? 114What is a testable circuit? 115What is the aim of scan insertion? 116What is fault coverage? What is defect part per million (DPPM)? 117Why is design for testability important for a product's financial success? 119What is chip power usage analysis? 120What are the major components of CMOS power consumption? 121What is power optimization? 123What is VLSI physical design? 123What are the problems that make VLSI physical design so challenging? 124What is floorplanning? 128What is the placement process? 131What is the routing process? 133What is a power network? 135What is clock distribution? 139What are the key requirements for constructing a clock tree? 143What is the difference between time skew and length skew in a clock tree? 145What is scan chain? 149What is scan chain reordering? 151What is parasitic extraction? 152What is delay calculation? 155What is back annotation? 156What kind of signal integrity problems do place and route tools handle? 156What is cross-talk delay? 157What is cross-talk noise? 158What is IR drop? 159What are the major netlist formats for design representation? 162What is gate-level logic verification before tapeout? 162What is equivalence check? 163What is timing verification? 164What is design constraint? 165What is static timing analysis (STA)? 165What is simulation approach on timing verification 169What is the logical-effort-based timing closure approach? 173What is physical verification? 178What are design rule check (DRC), design verification (DV), and geometry verification (GV)? 179What is schematic verification (SV) or layout versus schematic (LVS)? 181What is automatic test pattern generation (ATPG)? 182What is tapeout? 184What is yield? 184What are the qualities of a good IC implementation designed? 187Conclusion 189Acronyms 191Bibliography 195Index 199
