A VHDL Synthesis Primer
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Describes the synthesis of VHDL into logic gates. Describes constructs that are supported for synthesis. This second edition uses the IEEE standard packages NUMERIC_BIT and NUMERIC_STD and includes many more examples than the first edition.
Preface Chapter 1 Language Basics 1.2. Design Units 1.7. Simulating a Model Chapter 2 Synthesis Basics 2.2. Synthesis in a Design Process 2.3. Value Holders for Hardware Modeling 2.4. Logic Value System 2.5. Computing Bit-widths 2.5.2. Type BIT_VECTOR 2.5.6. Signed and Unsigned Types Chapter 3 Mapping Statements to Gates 3.4. Relational Operators 3.6. Process Statement 3.7. If Statement 3.8.1. Inferring Latches from Case Statements 3.9. Loop Statement 3.12.1. Multiple Clocks Chapter 4 Model Optimizations 4.2. Conversion Functions 4.3. Type INTEGER 4.4. Common Subexpressions 4.5. Moving Code 4.10. Design Size 4.11. Using Parenthesis Chapter 5 Verification 5.11. Initialization Chapter 6 Modeling Hardware Elements for Synthesis 6.8. Latch with Asynchronous Preset and Clear 6.9. Modeling a Memory 6.10. Using a Pre-built Component 6.11. Writing Boolean Equations 6.12. Modeling a Finite State Machine 6.12.2. Mealy FSM 6.12.3. Encoding States
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