Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation
This book constitutes the refereed proceedings of the 12th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2002, held in Seville, Spain in September 2002.\ The 37 revised full papers and 12 poster papers presented were carefully reviewed and selected from numerous submissions. The papers are organized in topical sections on arithmetics, low-level modeling and characterization, asynchronous and adiabatic techniques, CAD tools and algorithms, timing,...
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This book constitutes the refereed proceedings of the 12th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2002, held in Seville, Spain in September 2002.The 37 revised full papers and 12 poster papers presented were carefully reviewed and selected from numerous submissions. The papers are organized in topical sections on arithmetics, low-level modeling and characterization, asynchronous and adiabatic techniques, CAD tools and algorithms, timing, gate-level modeling and design, and communications modeling and activity reduction.
The First Quartz Electronic Watch1An Improved Power Macro-Model for Arithmetic Datapath Components16Performance Comparison of VLSI Adders Using Logical Effort25MDSP: A High-Performance Low-Power DSP Architecture35Impact of Technology in Power-Grid-Induced Noise45Exploiting Metal Layer Characteristics for Low-Power Routing55Crosstalk Measurement Technique for CMOS ICs65Instrumentation Set-up for Instruction Level Power Modeling71Low-Power Asynchronous A/D Conversion81Optimal Two-Level Delay - Insensitive Implementation of Logic Functions92Resonant Multistage Charging of Dominant Capacitances101A New Methodology to Design Low-Power Asynchronous Circuits108Designing Carry Look-Ahead Adders with an Adiabatic Logic Standard-Cell Library118Clocking and Clocked Storage Elements in Multi-GHz Environment128Dual Supply Voltage Scaling in a Conventional Power-Driven Logic Synthesis Environment146Transistor Level Synthesis Dedicated to Fast I.P. Prototyping156Robust SAT-Based Search Algorithm for Leakage Power Reduction167PA-ZSA (Power-Aware Zero-Slack Algorithm): A Graph-Based Timing Analysis for Ultra-Low Power CMOS VLSI178A New Methodology for Efficient Synchronization of RNS-Based VLSI Systems188Clock Distribution Network Optimization under Self-Heating and Timing Constraints198A Technique to Generate CMOS VLSI Flip-Flop Based on Differential Latches209A Compact Charge-Based Propagation Delay Model for Submicronic CMOS Buffers219Output Waveform Evaluation of Basic Pass Transistor Structure229An Approach to Energy Consumption Modeling in RC Ladder Circuits239Structure Independent Representation of Output Transition Time for CMOS Library247A Low Energy Clustered Instruction Memory Hierarchy for Long Instruction Word Processors258Design and Realization of a Low Power Register File Using Energy Model268Register File Energy Reduction by Operand Data Reuse278Energy-Efficient Design of the Recorder Buffer289Trends in Ultralow-Voltage RAM Technology300Office Data Profiling Techniques to Enhance Memory Compression in Embedded Systems314Performance and Power Comparative Study of Discrete Wavelet Transform on Programmable Processors323Power Consumption Estimation of a C Program for Data-Intensive Applications332A Low Overhead Auto-Optimizing Bus Encoding Scheme for Low Power Data Transmission342Measurement of the Switching Activity of CMOS Digital Circuits at the Gate Level353Low-Power FSMs in FPGA: Encoding Alternatives363Synthetic Generation of Events for Address-Event-Representation Communications371Reducing Energy Consumption via Low-Cost Value Prediction380Dynamic Voltage Scheduling for Real Time Asynchronous Systems390Efficient and Fast Current Curve Estimation of CMOS Digital Circuits at the Logic Level400Power Efficient Vector Quantization Design Using Pixel Truncation409Minimizing Spurious Switching Activities in CMOS Circuits419Modeling Propagation Delay of MUX, XOR, and D-Latch Source-Coupled Logic Gates429Operating Region Modelling and Timing Analysis of CMOS Gates Driving Transmission Lines438Selective Clock-Gating for Low Power/Low Noise Synchronous Counters 1448Probabilistic Power Estimation for Digital Signal Processing Architectures458Modeling of Propagation Delay of a First Order Circuit with a Ramp Input468Characterization of Normal Propagation Delay for Delay Degradation Model (DDM)477Automated Design Methodology for CMOS Analog Circuit Blocks in Complex Systems487Author Index495
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