Sequential Logic Testing And Verification
Search in google:
\ BooknewsA detailed treatment of recent advances in test generation and verification methods for synchronous, sequential logic circuits, intended for designers of integrated circuits and for researchers in logic synthesis, testing, and formal verification. Among the topics are test generation using RTL descriptions, sequential synthesis for testability, and symbolic FSM traversal methods. Annotation c. Book News, Inc., Portland, OR (booknews.com)\ \
![Mastering AutoCAD 2010 and AutoCAD LT 2010 [With DVD ROM]](/application/data/covers/60/32/9780470466032.jpg "Mastering AutoCAD 2010 and AutoCAD LT 2010 [With DVD ROM]")
