Timing Analysis and Optimization of Sequential Circuits
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Recent years have seen rapid strides in the level of sophistication of VLSI circuits. On the performance front, there is a vital need for techniques to design fast, low-power chips with minimum area for increasingly complex systems, while on the economic side there is the vastly increased pressure of time-to-market. These pressures have made the use of CAD tools mandatory in designing complex systems. Timing Analysis and Optimization of Sequential Circuits describes CAD algorithms for analyzing and optimizing the timing behavior of sequential circuits with special reference to performance parameters such as power and area. A unified approach to performance analysis and optimization of sequential circuits is presented. The state of the art in timing analysis and optimization techniques is described for circuits using edge-triggered or level-sensitive memory elements. Specific emphasis is placed on two methods that are true sequential timing optimizations techniques: retiming and clock skew optimization. Timing Analysis and Optimization of Sequential Circuits covers the following topics: Algorithms for sequential timing analysis Fast algorithms for clock skew optimization and their applications Efficient techniques for retiming large sequential circuits Coupling sequential and combinational optimizations. Timing Analysis and Optimization of Sequential Circuits is written for graduate students, researchers and professionals in the area of CAD for VLSI and VLSI circuit design. Booknews One has to applaud a text for engineers in the area of CAD for VLSI circuit design that begins by stating that the authors "feel obligated to switch from the language of Dilbert cliches to plain English." In presenting a unified approach to designing fast, low power chips for increasingly complex systems, Maheshwari (Iowa State U.) and Sapatnekar (U. of Minnesota) overview techniques for analysis and performance optimization of combinational and sequential circuits; compare the assets and disadvantages of edge- triggered and level-triggered clocking disciplines; and discuss deliberate skews and retiming techniques to improve circuit behavior, offering some new algorithms. Annotation c. Book News, Inc., Portland, OR (booknews.com)
List of FiguresPreface1Introduction12Timing Analysis of Sequential Circuits73Clock Skew Optimization334The Basics of Retiming655Minarea Retiming996Retiming Control Logic1237Miscellaneous Issues in Retiming1478Conclusion169References171
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